1988 Microchip Technology Inc.
Preliminary
DS21113D-page 1
FEATURES
2.7V to 3.6V Supply
Read Access Time--300 ns
CMOS Technology for Low Power Dissipation
- 8 mA Active
- 50
A CMOS Standby Current
Byte Write Time--3 ms
Data Retention >200 years
High Endurance - Minimum 100,000 Erase/Write
Cycles
Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
Data Polling
Ready/Busy
Chip Clear Operation
Enhanced Data Protection
- V
CC
Detector
- Pulse Filter
- Write Inhibit
Electronic Signature for Device Identification
Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-In-Line Package
- 32-pin Chip Carrier (Leadless or Plastic)
Available for Extended Temperature Ranges:
- Commercial: 0C to +70C
- Industrial: -40C to +85C
DESCRIPTION
The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-
atile electrically Erasable PROM organized as 8K words by 8 bits.
The 28LV64A is accessed like a static RAM for the read or write
cycles without the need of external components. During a "byte
write", the address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Fol-
lowing the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an inter-
nal control timer. To determine when the write cycle is complete,
the user has a choice of monitoring the Ready/Busy output or
using Data polling. The Ready/Busy pin is an open drain output,
which allows easy configuration in `wired-or' systems. Alterna-
tively, Data polling allows the user to read the location last written
to when the write operation is complete. CMOS design and pro-
cessing enables this part to be used in systems where reduced
power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in applica-
tions.
PACKAGE TYPES
BLOCK DIAGRAM
Pin 1 indicator on PLCC on top of package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RDY/BSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
Vcc
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
SS
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
A7
A12
RDY/BSY
NU
Vcc
WE
NC
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
14
15
16
17
18
19
20
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
DIP/SOIC
PLCC
64K bit
Cell Matrix
Y Gating
Input/Output
Buffers
Data
Poll
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
Program Voltage
Generation
Y
Decoder
X
Decoder
L
a
t
c
h
e
s
A0
A12
I
I
I
I
I
I
I
I
I
I
I
VCC
VSS
CE
OE
WE
Rdy/
Busy
I/O0...................I/O7
28LV64A
64K (8K x 8) Low Voltage CMOS EEPROM
28LV64A
DS21113D-page 2
Preliminary
1988 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
MAXIMUM RATINGS*
VCC and input voltages w.r.t. V
SS
...... -0.6V to + 6.25V
Voltage on OE w.r.t. V
SS
...................... -0.6V to +13.5V
Voltage on A9 w.r.t. V
SS
....................... -0.6V to +13.5V
Output Voltage w.r.t. V
SS
.................-0.6V to VCC+0.6V
Storage temperature .......................... -65C to +150C
Ambient temp. with power applied......-55
C to +125
C
*Notice: Stresses above those listed under "Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is
not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
TABLE 1-1:
PIN FUCTION TABLE
Name
Function
A0 - A12
Address Inputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
RDY/Busy
Ready/Busy
V
CC
+ Power Supply
V
SS
Ground
NC
No Connect; No Internal Connection
NU
Not Used; No External Connection is
Allowed
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTICS
V
CC
= 2.7 to 3.6V
Commercial (C): Tamb =
0
C to 70
C
Industrial
(I): Tamb = -40
C to 85
C
Parameter
Status
Symbol
Min
Max
Units Conditions
Input Voltages
Logic "1"
Logic "2"
V
IH
V
IL
2.0
0.6
V
V
Input Leakage
--
I
LI
--
5
A
V
IN
= 0V to V
CC
+1
Input Capacitance
--
C
IN
--
6
pF
Vin = 0V; Tamb = 25
C;
f = 1 MHz (Note 1)
Output Voltages
Logic "1"
Logic "0"
V
OH
V
OL
2.0
0.3
V
V
I
OH
= -100A
I
OL
= 1.0 mA
I0
L
= 2.0 mA for RDY/Busy
Output Leakage
--
I
LO
--
5
A
V
OUT
= 0V to V
CC
+0.1V
Output Capacitance
--
C
OUT
--
12
pF
V
OUT
= 0V; Tamb = 25
C;
f = 1 MHz (Note 1)
Power Supply Current, Activity
TTL input
I
CC
--
8
mA
f = 5 MHz (Note 2)
I
O
= OmA
V
CC
= 3.3
CE = V
IL
Power Supply Current, Standby
TTL input
TTL input
CMOS input
I
CC
(
S
)
TTL
I
CC
(
S
)
TTL
I
CC
(
S
)
CMOS
--
2
3
100
mA
mA
A
CE = V
IH
(0
C to 70
C
)
CE = V
IH
(-40
C to 85
C
)
CE = V
CC
-3.0 to V
CC
+1
OE = WE = V
CC
All other inputs equal V
CC
or
V
SS
Note 1: Not 100% tested.
2: AC power supply current above 5 MHz: 2 mA/Mhz.
1988 Microchip Technology Inc.
Preliminary
DS21113D-page 3
28LV64A
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
FIGURE 1-1:
READ WAVEFORMS
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
V
IH
= 2.0V; V
IL
= 0.6V; V
OH
= V
OL
= V
CC
/2
1 TTL Load + 100 pF
20 ns
Commercial (C): Tamb = 0
C to +70
C
Industrial (I) : Tamb = -40
C to +85
C
Parameter
Sym
28LV64-30
Units
Conditions
Min
Max
Address to Output Delay
t
ACC
--
300
ns
OE = CE = V
IL
CE to Output Delay
t
CE
--
300
ns
OE = V
IL
OE to Output Delay
t
OE
--
150
ns
CE = V
IL
CE or OE High to Output Float
t
OFF
0
60
ns
(Note 1)
Output Hold from Address, CE or
OE, whichever occurs first.
t
OH
0
--
ns
(Note 1)
Endurance
--
10M
--
cycles
25C, Vcc = 5.0V,
Block Mode (Note 2)
Note 1: Not 100% tested.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
Address
CE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
OE
Data
WE
V
OH
V
OL
V
IH
V
IL
Address Valid
High Z
Valid Output
t
ACC
(1) t
OFF
is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
(3) This parameter is sampled and is not 100% tested
High Z
t
OH
t
OFF(1,3)
Notes:
t
OE(2)
t
CE(2)
28LV64A
DS21113D-page 4
Preliminary
1988 Microchip Technology Inc.
TABLE 1-4:
BYTE WRITE AC CHARACTERISTICS
FIGURE 1-2:
PROGRAMMING WAVEFORMS
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
V
IH
= 2.0V; V
IL
= 0.6V; V
OH
= V
OL
= V
CC
/2
1 TTL Load + 100 pF
20 ns
Commercial (C): Tamb = 0
C to +70
C
Industrial (I) : Tamb = -40
C to +85
C
Parameter
Sym
Min
Max
Units
Remarks
Address Set-Up Time
t
AS
10
ns
Address Hold Time
t
AH
100
ns
Data Set-Up Time
t
DS
120
ns
Data Hold Time
t
DH
10
ns
Write Pulse Width
t
WPL
150
ns
(Note 1)
OE Hold Time
t
OEH
10
ns
OE Set-Up Time
t
OES
10
ns
Data Valid Time
t
DV
1000
ns
(Note 2)
Time to Device Busy
t
DB
50
ns
Write Cycle Time (28LV64A)
t
WC
3
ms
1.5 ms typical
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the
positive edge of CE or WE, whichever occurs first.
2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until t
DH
after the positive edge of WE or CE, whichever occurs first.
V
IH
V
IL
V
IH
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IL
twc
t
DB
t
OEH
t
OES
t
DH
t
DS
t
WPL
t
AH
t
AS
t
DV
Busy
Ready
Rdy/Busy
OE
Data In
Address
CE, WE
1988 Microchip Technology Inc.
Preliminary
DS21113D-page 5
28LV64A
FIGURE 1-3:
DATA POLLING WAVEFORMS
FIGURE 1-4:
CHIP CLEAR WAVEFORMS
TABLE 1-5:
SUPPLEMENTARY CONTROL
Mode
CE
OE
WE
A
I
V
CC
I/O
I
Chip Clear
V
IL
V
H
X
V
CC
Extra Row Read
V
IL
V
IL
V
IH
A9 = V
H
V
CC
Data Out
Extra Row Write
V
IH
A9 = V
H
V
CC
Data In
Note:
V
H
= 12.0V 0.5V
Address Valid
Last Written
Address Valid
t
ACC
t
CE
t
WPL
t
WPH
t
DV
t
WC
t
OE
True Data Out
Data In
Valid
V
IH
V
IL
Data
OE
WE
CE
Address
I/O7 Out
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
H
V
IH
CE
OE
WE
t
S
t
H
t
W
t
S
= = 1s
t
H
= 10ms
t
W
V
IH
V
IL
V
IH
V
IL
= 12.0V 0.5V
V
H
28LV64A
DS21113D-page 6
Preliminary
1988 Microchip Technology Inc.
2.0
DEVICE OPERATION
The Microchip Technology Inc. 28LV64A has four
basic modes of operation--read, standby, write inhibit,
and byte write--as outlined in the following table.
2.1
Read Mode
The 28LV64A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to
the output pins independent of device selection.
Assuming that addresses are stable, address access
time (t
ACC
) is equal to the delay from CE to output
(tCE). Data is available at the output t
OE
after the fall-
ing edge of OE, assuming that CE has been low and
addresses have been stable for at least t
ACC
-t
OE
.
2.2
Standby Mode
The 28LV64A is placed in the standby mode by apply-
ing a high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state, inde-
pendent of the OE input.
2.3
Data Protection
In order to ensure data integrity, especially during criti-
cal power-up and power-down transitions, the follow-
ing enhanced data protection circuits are incorporated:
First, an internal V
CC
detect (2.0 volts typical) will
inhibit the initiation of non-volatile programming opera-
tion when V
CC
is less than the V
CC
detect circuit trip.
Second, holding WE or CE high or OE low, inhibits a
write cycle during power-on and power-off (V
CC
).
Operation Mode
Read
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
CE
L
H
H
X
X
L
OE
L
X
X
L
X
H
WE
H
X
X
X
H
L
I/O
D
OUT
High Z
High Z
High Z
High Z
D
IN
Automatic Before Each "Write"
Rdy/Busy
(1)
H
H
H
H
H
L
Note: (1) Open drain output.
2.4
Write Mode
The 28LV64A has a write cycle similar to that of a
static RAM. The write cycle is completely self-timed
and initiated by a low going pulse on the WE pin. On
the falling edge of WE, the address information is
latched. On rising edge, the data and the control pins
(CE and OE) are latched. The Ready/Busy pin goes
to a logic low level indicating that the 28LV64A is in a
write cycle which signals the microprocessor host that
the system bus is free for other activity. When
Ready/Busy goes back to a high, the 28LV64A has
completed writing and is ready to accept another
cycle.
2.5
Data Polling
The 28LV64A features Data polling to signal the com-
pletion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the
data complement of I/O7 (I/O0 to I/O6 can not be
determined). After completion of the write cycle, true
data is available. Data polling allows a simple
read/compare operation to determine the status of the
chip eliminating the need for external hardware.
2.6
Electronic Signature for Device
Identification
An extra row of 32 bytes of EEPROM memory is avail-
able to the user for device identification. By raising A9
to 12V
0.5V and using address locations 1FEO to
1FFF, the additional bytes can be written to or read
from in the same manner as the regular memory array.
2.7
Chip Clear
All data may be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE
low. This procedure clears all data, except for the
extra row.
28LV64A
28LV64A Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
Package:
L = Plastic Leaded Chip Carrier (PLCC)
P = Plastic DIP
SO = Plastic Small Outline IC
Temperature
Blank = 0C to +70C
Range:
I = -40C to +85C
Access Time:
20 = 200 ns
30 - 300 ns
Shipping:
Blank = Tube
T
= Tape and Reel "L" and "SO"
Option:
Blank = twc = 1ms
F = twc = 200s
Device:
24LV64A
8K x 8 CMOS EEPROM
28LV64A
F T 20 I /P
1988 Microchip Technology Inc.
DS21113D-page 7
2002 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip's products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
K
EE
L
OQ
, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company's quality system processes and
procedures are QS-9000 compliant for its
PICmicro
8-bit MCUs, K
EE
L
OQ
code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip's quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Note the following details of the code protection feature on PICmicro
MCUs.
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as "unbreakable".
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
2002 Microchip Technology Inc.
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Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02
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